1.9 Ethernet

The SAM E54 Curiosity Ultra development kit has a modular Ethernet PHY system that enables different PHYs to be plugged into the board. This interface is setup to use a Reduced Media-Independent Interface (RMII) and a SPI bus interface with GPIO. The following figure illustrates the Ethernet PHY header configuration.

Figure 1-6. Ethernet PHY Header Configuration

The following table provides the Ethernet PHY interface pinout descriptions.

Table 1-9. Ethernet Interface Pinout Description
Pin NumberNameDescription
1GPIOGeneral purpose I/O
2GPIOGeneral purpose I/O
3RXD1Receive Data 1
4RXD0Receive Data 0
5RXERReceive Error
6RXDVReceive Data Valid
7MDC-
8MDIO-
9IRQInterrupt request line
10RESETReset control to the Ethernet PHY
11GPIOGeneral purpose I/O
12EGNDShield Ground
13 (1)TXENTransmit Enable
14 (2)TXD0Transmit Data
15 (3)TDX1Transmit Data
16 (4)MOSIHost Out Client In line of serial peripheral interface
17 (5)MISOHost In Client Out line of serial peripheral interface
18 (6)GNDGround
19 (7)NCNo Connect
20 (8)REFCLK (in)Reference Clock input (50 MHz)
21 (9)GNDGND
22 (10)+3.3v VDD+3.3V VDD
23 (11)CSChip Select for serial peripheral interface
24 (12)SCKClock for serial peripheral interface
25 -30EGNDShield Ground