3 Pin Allocation Tables

Table 3-1. 8-Pin Allocation Table
I/O8-Pin

PDIP

SOIC

ADCDACComparatorZCDTimersCCP16-Bit

PWM

CWGCLCMSSPEUSARTIOCInterruptBasic
RA07ANA0(4)DAC1OUT1C1IN0+T3CKI(1)

T3G(1)

T4IN(1)

PWMIN0(1)

PWMIN1(1)

PWM2ERS(1)

CLCIN3(1)SCL2(1,3)

SCK2(1,3)

SDA2(1,3)

SDI2(1,3)

SS2(1)

CK1(1,3)

CK2(1,3)

IOCA0ICSPDAT

ICDDAT

RA16ANA1(4)

VREF+ (ADC)

DAC1REF0+

DAC2REF0+

C1IN0-CLCIN2(1)SCL1(1,3)

SCK1(1,3)

RX1(1)

DT1(1,3)

RX2(1)

DT2(1,3)

IOCA1ICSPCLK

ICDCLK

RA25

ANA2(4)

DAC1REF0-

DAC2REF0-

ZCD1T0CKI(1)CWG1(1)SDA1(1,3)

SDI1(1,3)

IOCA2INT(1)
RA34CLCIN0 (1)SS1(1)IOCA3MCLR

VPP

RA43

ANA4(4)

C1IN1-T1G(1)IOCA4

CLKOUT

OSC2

SOSCO

RA52ANA5(4)

ADACT(1)

T1CKI(1)

T2IN(1)

CCP1(1)

CCP2(1)

PWM1ERS(1)CLCIN1(1)IOCA5

CLKIN

OSC1

SOSCI

VDD1VDD
VSS8VSS
OUT(2)

ADGRDA

ADGRDB

CMP1

CMP2

TMR0CCP1

CCP2

PWM11

PWM12

PWM21

PWM22

CWG1A

CWG1B

CWG1C

CWG1D

CLC1OUT

CLC2OUT

CLC3OUT

CLC4OUT

SCL1

SCK1

SDA1

SDO1

SCL2

SCK2

SDA2

SDO2

TX1

DT1

CK1

TX2

DT2

CK2

Note:
  1. This is a PPS remappable input signal. The input function may be moved from the default location shown to any PORTx pin.
  2. All output signals shown in this row are PPS remappable.
  3. This is a bidirectional signal. For normal operation, user software must map this signal to the same pin via the PPS input and PPS output registers.
  4. This pin can be used as either a positive or negative analog input channel to the ADC.
Table 3-2. 14/16-Pin Allocation Table
I/O14-Pin

PDIP

SOIC

TSSOP

16-Pin

VQFN

ADCDACComparatorZCDTimersCCP16-Bit

PWM

CWGCLCMSSPEUSARTIOCInterruptBasic
RA01312

ANA0(5)

DAC1OUT1C1IN0+

SS2(1)

IOCA0ICSPDAT

ICDDAT

RA11211

ANA1(5)

VREF+(ADC)

DAC1REF0+

DAC2REF0+

C1IN0-

C2IN0-

IOCA1ICSPCLK

ICDCLK

RA21110

ANA2(5)

DAC1REF0-

DAC2REF0-

DAC1OUT2

ZCD1T0CKI(1)CWG1(1)IOCA2INT(1)
RA343IOCA3MCLR

VPP

RA432

ANA4(5)

T1G(1)IOCA4

CLKOUT

OSC2

SOSCO

RA521

ANA5(5)

T1CKI(1)

T2IN(1)

PWM1ERS(1)CLCIN3(1)IOCA5

CLKIN

OSC1

SOSCI

RC0109

ANC0(5)

C2IN0+SCL1(1,3,4)

SCK1(1,3,4)

CK2(1,3)IOCC0
RC198

ANC1(5)

C1IN1-

C2IN1-

T4IN(1)

PWM2ERS(1)CLCIN2(1)SDA1(1,3,4)

SDI1(1,3,4)

RX2(1)

DT2(1,3)

IOCC1
RC287ANC2(5)

ADACT(1)

C1IN2-

C2IN2-

IOCC2
RC376

ANC3(5)

C1IN3-

C2IN3-

CCP2(1)PWMIN1(1)CLCIN0(1)SS1(1)IOCC3
RC465

ANC4(5)

T3G(1)CLCIN1(1)

SCK2(1,3,4)

SCL2(1,3,4)

CK1(1,3)IOCC4
RC554

ANC5(5)

T3CKI(1)CCP1(1)PWMIN0(1)

SDA2(1,3,4)

SDI2(1,3,4)

RX1(1)

DT1(1,3)

IOCC5
VDD116VDD
VSS1413VSS
OUT(2)

ADGRDA

ADGRDB

CMP1

CMP2

TMR0CCP1

CCP2

PWM11

PWM12

PWM21

PWM22

CWG1A

CWG1B

CWG1C

CWG1D

CLC1OUT

CLC2OUT

CLC3OUT

CLC4OUT

SCL1

SCK1

SDA1

SDO1

SCL2

SCK2

SDA2

SDO2

TX1

DT1

CK1

TX2

DT2

CK2

Note:
  1. This is a PPS remappable input signal. The input function may be moved from the default location shown to any PORTx pin.
  2. All output signals shown in this row are PPS remappable.
  3. This is a bidirectional signal. For normal operation, user software must map this signal to the same pin via the PPS input and PPS output registers.
  4. These pins can be configured for I2C or SMBus logic levels via the RxyI2C registers. The SCL1/SDA1 signals may be assigned to these pins for expected operation. PPS assignments of these signals to other pins will operate; however, the logic levels will be standard TTL/ST as selected by the INLVL register.
  5. This pin can be used as either a positive or negative analog input channel to the ADC.
Table 3-3. 20-Pin Allocation Table
I/O20-Pin

PDIP

SOIC

SSOP

20-Pin

VQFN

ADCDACComparatorZCDTimersCCP16-Bit

PWM

CWGCLCMSSPEUSARTIOCInterruptBasic
RA01916

ANA0(5)

DAC1OUT1C1IN0+IOCA0ICSPDAT

ICDDAT

RA11815

ANA1(5)

VREF+(ADC)

DAC1REF0+

DAC2REF0+

C1IN0-

C2IN0-

SS2(1)

IOCA1ICSPCLK

ICDCLK

RA21714

ANA2(5)

DAC1REF0-

DAC2REF0-

DAC1OUT2

ZCD1T0CKI(1)CWG1(1)CLCIN0(1)IOCA2INT(1)
RA341IOCA3MCLR

VPP

RA4320

ANA4(5)

T1G(1)IOCA4

CLKOUT

OSC2

SOSCO

RA5219

ANA5(5)

T1CKI(1)

T2IN(1)

PWM1ERS(1)IOCA5

CLKIN

OSC1

SOSCI

RB41310

ANB4(5)

CLCIN2(1)SDA1(1,3,4)

SDI1(1,3,4)

IOCB4
RB5129

ANB5(5)

CLCIN3(1)

SDA2(1,3,4)

SDI2(1,3,4)

RX1(1)

DT1(1,3)

IOCB5
RB6118

ANB6(5)

SCL1(1,3,4)

SCK1(1,3,4)

IOCB6
RB7107ANB7(5)

SCL2(1,3,4)

SCK2(1,3,4)

CK1(1,3)IOCB7
RC01613ANC0(5)C2IN0+CK2(1,3)IOCC0
RC11512ANC1(5)C1IN1-

C2IN1-

T4IN(1)PWM2ERS(1)RX2(1)

DT2(1,3)

IOCC1
RC21411ANC2(5)

ADACT(1)

C1IN2-

C2IN2-

IOCC2
RC374ANC3(5)C1IN3-

C2IN3-

CCP2(1)PWMIN1(1)CLCIN1(1)IOCC3
RC463ANC4(5)T3G(1)IOCC4
RC552ANC5(5)T3CKI(1)CCP1(1)PWMIN0(1)IOCC5
RC685ANC6(5)SS1(1)IOCC6
RC796ANC7(5)IOCC7
VDD118VDD
VSS2017VSS
OUT(2)ADGRDA

ADGRDB

CMP1

CMP2

TMR0CCP1

CCP2

PWM11

PWM12

PWM21

PWM22

CWG1A

CWG1B

CWG1C

CWG1D

CLC1OUT

CLC2OUT

CLC3OUT

CLC4OUT

SCL1

SCK1

SDA1

SDO1

SCL2

SCK2

SDA2

SDO2

TX1

DT1

CK1

TX2

DT2

CK2

Note:
  1. This is a PPS remappable input signal. The input function may be moved from the default location shown to any PORTx pin.
  2. All output signals shown in this row are PPS remappable.
  3. This is a bidirectional signal. For normal operation, user software must map this signal to the same pin via the PPS input and PPS output registers.
  4. These pins can be configured for I2C or SMBus logic levels via the RxyI2C registers. The SCL1/SDA1 signals may be assigned to these pins for expected operation. PPS assignments of these signals to other pins will operate; however, the logic levels will be standard TTL/ST as selected by the INLVL register.
  5. This pin can be used as either a positive or negative analog input channel to the ADC.