48.6.1 Control A
| Name: | CTRLA |
| Offset: | 0x00 |
| Reset: | 0x00 |
| Property: | PAC Write-Protection |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RUNSTDBY | ENABLE | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
Bit 6 – RUNSTDBY Run in Standby
This bit controls how the ADC behaves during standby sleep mode:
| Value | Description |
|---|---|
| 0 | The TRNG is halted during standby sleep mode. |
| 1 | The TRNG is not stopped in standby sleep mode. |
Bit 1 – ENABLE Enable
Note: A delay between TRNG Enable (CTRLA.ENABLE=1) and the first random number read is
required. Refer to the TRNG Electrical Specifications.
| Value | Description |
|---|---|
| 0 | The TRNG is disabled. |
| 1 | The TRNG is enabled. |