19.6.5.3.1 BOD33 Sampling Mode

The sampling mode is a Low-Power mode where the BOD33 is being repeatedly enabled on a sampling clock’s ticks. The BOD33 will monitor the supply voltage (VDD or VBAT) for a short period of time and then go to a low-power disabled state until the next sampling clock tick.

Sampling mode is enabled in Backup or Hibernate mode by writing to the BOD33 bits (BOD33.BKUPCFG = 1 or BOD33.HIBCFG = 1). The frequency of the clock ticks (Fclksampling) is controlled by the Prescaler Select bit groups in the BOD33 register (BOD33.PSEL).

F c l k s a m p l i n g = F c l k p r e s c a l e r 2 ( PSEL+1 )

The prescaler signal (Fclkprescaler) is a 32.768 kHz clock, output by the 32 kHz Ultra Low-Power Oscillator OSCULP32K.

Note: If (BOD33.PSEL) is 0, sampling mode is disabled.

As the sampling clock is different from the APB clock domain, synchronization among the clocks is necessary. See 19.6.7 Synchronization for additional information.