30.6.9 Channel n Interrupt Enable Clear

Name: CHINTENCLR
Offset: 0x24 + n*0x08 [n=0..11]
Reset: 0x00
Property: PAC Write-Protection

Bit 76543210 
       EVDOVR 
Access RWRW 
Reset 00 

Bit 1 – EVD Channel Event Detected Interrupt Disable

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will clear the Event Detected Channel Interrupt Enable bit, which disables the Event Detected Channel interrupt.

ValueDescription
0 The Event Detected Channel interrupt is disabled.
1 The Event Detected Channel interrupt is enabled.

Bit 0 – OVR Channel Overrun Interrupt Disable

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will clear the Overrun Channel Interrupt Enable bit, which disables the Overrun Channel interrupt.

ValueDescription
0 The Overrun Channel interrupt is disabled.
1 The Overrun Channel interrupt is enabled.