18.6.6 Interrupts

The OSCCTRL has the following interrupt sources:

• XOSCRDYN - Multipurpose Crystal Oscillator Ready: A 0-to-1” transition on the STATUS.XOSCRDY bit is detected
• XOSCFAILN - Clock Failure . A “0-to-1” transition on the STATUS.XOSCFAILN bit is detected
• DFLLRDY - DFLL48m Ready: A “0-to-1” transition on the STATUS.DFLLRDY bit is detected
• DFLLOOB - DFLL Out of Bounds: A "0-to-1" transition on STATUS.DFLLOOB detected
• DFLLCKF - DFLL Lock Fine: A "0-to-1" transition on STATUS.DFLLCKF detected
• DFLLCKC - DFLL Lock Coarse: A "0-to-1" transition on STATUS.DFLLCKC detected
• DPLLnLCKR - DPLLn Lock Rise: A “0-to-1” transition on the STATUS.DPLLnLCKR bit is detected
• DPLLnLCKF - DPLLn Lock Fall: A “0-to-1” transition on the STATUS.DPLLnLCKF bit is detected
• DPLLnLTTO - DPLLn Lock Timer Time-out: A “0-to-1” transition on the STATUS.DPLLnLTTO bit is detected
• DPLLnLDRTO - DPLLn Loop Divider Ratio Update Complete

Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG) is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a one to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing a one to the corresponding bit in the Interrupt Enable Clear register (INTENCLR). An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled, or the OSCCTRL is reset. INTFLAG register for details on how to clear interrupt flags.

The OSCCTRL has one common interrupt request line for all the interrupt sources. The user must read the INTFLAG register to determine which interrupt condition is present.

Note that interrupts must be globally enabled for interrupt requests to be generated.