18.7 Register Summary
Offset | Name | Bit Pos. | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|
0x00 | EVCTRL | 7:0 | CFDEO1 | CFDEO0 | ||||||
0x01 ... 0x03 | Reserved | |||||||||
0x04 | INTENCLR | 7:0 | XOSCFAIL1 | XOSCFAIL0 | XOSCRDY1 | XOSCRDY0 | ||||
15:8 | DFLLRCS | DFLLLCKC | DFLLLCKF | DFLLOOB | DFLLRDY | |||||
23:16 | DPLL0LDRTO | DPLL0LTO | DPLL0LCKF | DPLL0LCKR | ||||||
31:24 | DPLL1LDRTO | DPLL1LTO | DPLL1LCKF | DPLL1LCKR | ||||||
0x08 | INTENSET | 7:0 | XOSCFAIL1 | XOSCFAIL0 | XOSCRDY1 | XOSCRDY0 | ||||
15:8 | DFLLRCS | DFLLLCKC | DFLLLCKF | DFLLOOB | DFLLRDY | |||||
23:16 | DPLL0LDRTO | DPLL0LTO | DPLL0LCKF | DPLL0LCKR | ||||||
31:24 | DPLL1LDRTO | DPLL1LTO | DPLL1LCKF | DPLL1LCKR | ||||||
0x0C | INTFLAG | 7:0 | XOSCFAIL1 | XOSCFAIL0 | XOSCRDY1 | XOSCRDY0 | ||||
15:8 | DFLLRCS | DFLLLCKC | DFLLLCKF | DFLLOOB | DFLLRDY | |||||
23:16 | DPLL0LDRTO | DPLL0LTO | DPLL0LCKF | DPLL0LCKR | ||||||
31:24 | DPLL1LDRTO | DPLL1LTO | DPLL1LCKF | DPLL1LCKR | ||||||
0x10 | STATUS | 7:0 | XOSCCKSW1 | XOSCCKSW0 | XOSCFAIL1 | XOSCFAIL0 | XOSCRDY1 | XOSCRDY0 | ||
15:8 | DFLLRCS | DFLLLCKC | DFLLLCKF | DFLLOOB | DFLLRDY | |||||
23:16 | DPLL0TO | DPLL0LCKF | DPLL0LCKR | |||||||
31:24 | DPLL1TO | DPLL1LCKF | DPLL1LCKR | |||||||
0x14 | XOSCCTRL0 | 7:0 | ONDEMAND | RUNSTDBY | XTALEN | ENABLE | ||||
15:8 | ENALC | IMULT[3:0] | IPTAT[1:0] | LOWBUFGAIN | ||||||
23:16 | STARTUP[3:0] | SWBEN | CFDEN | |||||||
31:24 | CFDPRESC[3:0] | |||||||||
0x18 | XOSCCTRL1 | 7:0 | ONDEMAND | RUNSTDBY | XTALEN | ENABLE | ||||
15:8 | ENALC | IMULT[3:0] | IPTAT[1:0] | LOWBUFGAIN | ||||||
23:16 | STARTUP[3:0] | SWBEN | CFDEN | |||||||
31:24 | CFDPRESC[3:0] | |||||||||
0x1C | DFLLCTRLA | 7:0 | ONDEMAND | RUNSTDBY | ENABLE | |||||
0x1D ... 0x1F | Reserved | |||||||||
0x20 | DFLLCTRLB | 7:0 | WAITLOCK | BPLCKC | QLDIS | CCDIS | USBCRM | LLAW | STABLE | MODE |
0x21 ... 0x23 | Reserved | |||||||||
0x24 | DFLLVAL | 7:0 | FINE[7:0] | |||||||
15:8 | COARSE[5:0] | |||||||||
23:16 | DIFF[7:0] | |||||||||
31:24 | DIFF[15:8] | |||||||||
0x28 | DFLLMUL | 7:0 | MUL[7:0] | |||||||
15:8 | MUL[15:8] | |||||||||
23:16 | FSTEP[7:0] | |||||||||
31:24 | CSTEP[5:0] | |||||||||
0x2C | DFLLSYNC | 7:0 | DFLLMUL | DFLLVAL | DFLLCTRLB | ENABLE | ||||
0x2D ... 0x2F | Reserved | |||||||||
0x30 | DPLL0CTRLA | 7:0 | ONDEMAND | RUNSTDBY | ENABLE | |||||
0x31 ... 0x33 | Reserved | |||||||||
0x34 | DPLL0RATIO | 7:0 | LDR[7:0] | |||||||
15:8 | LDR[12:8] | |||||||||
23:16 | LDRFRAC[4:0] | |||||||||
31:24 | ||||||||||
0x38 | DPLL0CTRLB | 7:0 | REFCLK[2:0] | WUF | FILTER[3:0] | |||||
15:8 | DCOEN | DCOFILTER[2:0] | LBYPASS | LTIME[2:0] | ||||||
23:16 | DIV[7:0] | |||||||||
31:24 | DIV[10:8] | |||||||||
0x3C | DPLL0SYNCBUSY | 7:0 | DPLLRATIO | ENABLE | ||||||
15:8 | ||||||||||
23:16 | ||||||||||
31:24 | ||||||||||
0x40 | DPLL0STATUS | 7:0 | CLKRDY | LOCK | ||||||
15:8 | ||||||||||
23:16 | ||||||||||
31:24 | ||||||||||
0x44 | DPLL1CTRLA | 7:0 | ONDEMAND | RUNSTDBY | ENABLE | |||||
0x45 ... 0x47 | Reserved | |||||||||
0x48 | DPLL1RATIO | 7:0 | LDR[7:0] | |||||||
15:8 | LDR[12:8] | |||||||||
23:16 | LDRFRAC[4:0] | |||||||||
31:24 | ||||||||||
0x4C | DPLL1CTRLB | 7:0 | REFCLK[2:0] | WUF | FILTER[3:0] | |||||
15:8 | DCOEN | DCOFILTER[2:0] | LBYPASS | LTIME[2:0] | ||||||
23:16 | DIV[7:0] | |||||||||
31:24 | DIV[10:8] | |||||||||
0x50 | DPLL1SYNCBUSY | 7:0 | DPLLRATIO | ENABLE | ||||||
15:8 | ||||||||||
23:16 | ||||||||||
31:24 | ||||||||||
0x54 | DPLL1STATUS | 7:0 | CLKRDY | LOCK | ||||||
15:8 | ||||||||||
23:16 | ||||||||||
31:24 |