51.6.3.3 Host - Client Operation

ADC1 will serve as a Client of ADC0 by writing a '1' to the Client Enable bit in the Control A register of the ADC1 instance (ADC1.CTRLA.SLAVEEN). When enabled, GCLK_ADC0 clock and ADC0 controls are internally routed to the ADC1 instance.

In this mode of operation, the Client ADC1 is enabled by accessing the CTRLA register of the Host ADC0. In the same way, the Host ADC event inputs will be automatically routed to the Client ADC, meaning that the input events configuration must be done in the Host ADC (ADC0.EVCTRL).
Note: To enable DMA sequencing for the ADC1 (Client), the ADC0 (Host) must be enabled first (ADC0.CTRLA.ENABLE = 1) before DMA sequencing is enabled (ADC1.DSEQCTRL ! = 0).

ADC measurements can either start simultaneously on both ADCs, or be interleaved. The trigger mode selection is available in the Host ADC Control A register (ADC0.CTRLA.DUALSEL).

Note: The interleaved sampling is only usable in single conversion mode (ADC.CTRLB.FREERUN = 0).
To restart an interleaved sequence, the user can apply different options:
  • Flush the Host ADC (ADC0.SWTRIG.FLUSH = 1)
  • Disable/re-enable the Host ADC (ADC0.CTRLA.ENABLE)
  • Reset and reconfigure Host ADC (ADC0.CTRLA.SWRST = 1)
  • Enable the flush event (EVCTRL.FLUSHEI = 1)