51.6.3.2 DMA Sequencing

The ADC can sequence a series of conversion. When DMA sequencing is enabled, a set of ADC configuration registers can be automatically refreshed using the DMA controller.

Enabling DMA Sequencing

DMA Sequencing is enabled when at least one bit in the DMA Sequence Control register (DSEQCTRL) is '1'.

When this is the case, the BUSY status bit in the DMA Sequential Status register (DSEQSTAT.BUSY) is set to '1'.

Note: ADC DMA Sequencing operations are limited to DIV2, DIV4 and DIV8 prescalers configuration.

Disabling DMA Sequencing

DMA Sequencing is disabled when at least one of the following conditions is valid:
  • The ADC is disabled (CTRLA.ENABLE = 0).
  • The ADC is reset (CTRLA.SWRST = 1).
  • The DMA Sequence Control register (DSEQCTRL) is written '0' and the ongoing DMA sequence is completed.
  • The DMA Sequencing Stop bit in Input Control register is '1' (INPUTCTRL.DSEQSTOP = 1) and the ongoing DMA sequence is complete. One additional measurement will be done before the ADC is disabled.

When the DMA sequencing is disabled, the BUSY status bit in the DMA Sequential Status register (DSEQSTAT.BUSY) is cleared and the DMA trigger generation is disabled.

Note that if the DSEQCTRL register is written to a non-zero value, the DSEQSTOP bit in the INPUTCTRL register will be cleared and the sequencing operation will not be stopped.

Restarting DMA Sequencing

When the DSEQSTOP bit is set (INPUTCTRL.DSEQSTOP = 1) and the sequence is disabled (DSEQSTAT.BUSY=0), it is possible to restart the sequencing by enabling one of the following conditions:
  • Write the DSEQSTOP bit in Input Control register to zero (INPUTCTRL.DSEQSTOP = 0)
  • Apply a FLUSH software command (SWTRIG.FLUSH = 1)
  • Enable the flush event (EVCTRL.FLUSHEI). The sequence will restart when the flush event is received

DMA Sequencing Operation

Each ADC register that is part of the DMA sequencing has a separate enable bit in the DSEQCTRL register to indicate that this field should be part of the DMA sequencing. When an enable bit in DSEQCTRL is '1', the respective register will be updated when an access to DSEQDATA is decoded.

The DMA Sequencing (DSEQ) trigger request is generated when BUSY status bit is one (DSEQSTAT.BUSY=1), the ADC is idle or a new conversion starts, and one of the following condition is true:
  • Input Control or Control B bits in DMA Sequential Control register is '1' (DSEQCTRL.INPUTCTRL=1 or DSEQCTRL.CTRLB=1)
  • Reference Control, Sampling Time Control or Average Control bits in DMA Sequential Control register is set (DSEQCTRL.REFCTRL=1, DSEQCTRL.AVGCTRL=1 or DSEQCTRL.SAMPCTRL=1)
  • Window Monitor Upper Threshold or Window Monitor Lower Threshold bits in DMA Sequential Control register is set (DSEQCTRL.WINUT=1 or DSEQCTRL.WINLT=1)
  • Offset Correction or Gain Correction bits in DMA Sequential Control register is set (DSEQCTRL.GAINCORR=1 or DSEQCTRL.OFFSETCORR=1)
Note: When received, the DMA data must be written to DSEQDATA register only, and only 32-bit DMA access is supported.
If a field is not enabled for DMA update, the corresponding register update will be ignored when DSEQDATA register is written. The table below shows the DSEQ trigger generation condition and internal ADC registers refresh when the DSEQDATA register is written by the DMA.
Table 51-4. DSEQ Trigger Generation and Internal ADC Register updates
Condition Value Action when DMA writes to DSEQDATA
DSEQSTAT.REFCTRL or DSEQSTAT.SAMPCTRL 0
  • No DMA trigger is generated
  • No data in the memory must be reserved
DSEQSTAT.REFCTRL or DSEQSTAT.AVGCTRL or DSEQSTAT.SAMPCTRL 1
  • A DMA trigger is generated
  • One word (32-bit) must be reserved in the memory
  • REFCTRL ← DSEQDATA[7:0] if DSEQSTAT.REFCTRL = 1
  • AVGCTRL ← DSEQDATA[23:16] if DSEQSTAT.AVGCTRL = 1
  • SAMPCTRL ← DSEQDATA[31:24] if DSEQSTAT.SAMPCTRL = 1
DSEQSTAT.WINLT or DSEQSTAT.WINUT 0
  • No DMA trigger is generated
  • No data in the memory must be reserved
1
  • A DMA trigger is generated
  • One word (32-bit) must be reserved in the memory
  • WINLT ← DSEQDATA[15:0] if DSEQSTAT.WINLT = 1
  • WINUT ← DSEQDATA[31:16] if DSEQSTAT.WINUT = 1
DSEQSTAT.GAINCORR or DSEQSTAT.OFFSETCORR 0
  • No DMA trigger is generated
  • No data in the memory must be reserved
1
  • A DMA trigger is generated
  • One word (32-bit) must be reserved in the memory
  • GAINCORR ← DSEQDATA[15:0] if DSEQSTAT.GAINCORR = 1
  • OFFSETCORR ← DSEQDATA[31:16] if DSEQSTAT.OFFSETCORR = 1

The DMA Sequential Status register (DSEQSTAT) stores the remaining registers to be updated by the DMA. During a sequence and when a write access to the DSEQDATA register is detected, the DSEQSTAT bits which were source of the corresponding DSEQ trigger will be cleared. When all DSEQSTAT bits are zero (except BUSY bit), the DSEQCTRL register bits (except AUTOSTART) are copied into the DSEQSTAT register and a new DMA sequence is started when a new ADC conversion starts.

DMA Descriptor Setup and Data Memory Organization

When DMA sequencing is enabled, the DMA Controller (DMAC) must be configured in the following way:
  • Select 32-bit beat size transfer (DMAC.BTCTRL.BEATSIZE=WORD).
  • Enable the source address increment options (DMAC.BTCTRL.SRCINC = 1, DMAC.BTCTRL.STEPSEL = SRC, DMAC.BTCTRL.STEPSIZE = X1).
  • Disable the destination address increment (DMAC.BTCTRL.DSTINC=0).
  • Set the block transfer count value (DMAC.BTCNT).
  • Set the block transfer source address (DMAC.SRCADDR), as described in the DMAC Addressing section. The address corresponds to the memory section from where the DMA reads the data.
  • Select the ADC.DSEQDATA address as value for the block transfer destination address (DMAC.DSTADDR = ADC.DSEQDATA address).
  • Select the channel single transfer type (DMAC.CHCTRLA.BURSTLEN=SINGLE)
  • Select the channel burst trigger action (DMAC.CHCTRLA.TRIGACT=BURST)
  • Select the ADC DMA Sequencing trigger as channel trigger source (DMAC.CHCTRLA.TRIGSRC=DSEQ)
  • Enable optional channel interrupts (DMAC.CHINTENSET)
  • Enable the corresponding DMA channel (DMAC.CHCTRLA.ENABLE)

When an ADC condition is enabled to trigger a DMA transfer, one word (32-bit) will be read by the DMA from the memory source location. Since the source address is incrementing by 0x1, the data memory must be organized in a contiguous memory area. As consequence, if an ADC group of registers does not generate any DMA trigger, no data must be reserved in the memory area for this register group. The next figure shows an example of memory organization when all ADC registers are part of the sequence, and a second example where WINLT and WINUT registers are not part of the sequence.

Automatic Start Conversion

By default, a new conversion starts when a new start software or event trigger is received. It is also possible to automatically enable an ADC conversion by writing '1' to the AUTOSTART bit in DSEQCTRL register (DSEQCTRL.AUTOSTART). When set, the ADC automatically starts a new conversion when a DMA sequence is complete.

Note: If averaging or oversampling is enabled, the new conversion automatically starts only when the previous RESULT is available (averaging or oversampling operation is complete).
Note: Free run mode (CTRLB.FREERUN=1) can not be used with DMA sequencing.
Note: If the conversion is triggered by event (EVCTRL.STARTEI=1), the automatic start conversion is disabled and the AUTOSTART settings are ignored.