32.6.4 DMA, Interrupts and Events
| Condition | Request | ||
|---|---|---|---|
| DMA | Interrupt | Event | |
| Data Register Empty (DRE) | Yes (request cleared when data is written) |
Yes | N/A |
| Receive Complete (RXC) | Yes (request cleared when data is read) |
Yes | |
| Transmit Complete (TXC) | N/A | Yes | |
| Receive Start (RXS) | N/A | Yes | |
| Clear to Send Input Change (CTSIC) | N/A | Yes | |
| Receive Break (RXBRK) | N/A | Yes | |
| Error (ERROR) | N/A | Yes | |