27.2 Features

The following are key features of the NVMCTRL module:

  • Two 32-bit AHB interfaces for reads and writes in the NVM main address space
  • SmartEEPROM (integrated EEPROM emulation algorithm)
  • Read-while-write (Any bank can be read while programming the other one)
  • All NVM sections are memory mapped to the AHB, including calibration and system configuration
  • 32-bit APB interface for commands and control
  • Programmable wait states for read optimization
  • 32 regions can be individually protected or unprotected
  • Additional protection for boot loader
  • Supports device protection through a security bit
  • Interface to Power Manager to power-down Flash blocks while in sleep modes
  • Can optionally wake up on exit from sleep or on first access
  • Single line cache per AHB interface
  • Dual bank for safer application upgrade
  • Immutable Boot support using Chip Erase Hard Lock, Boot Protect Hard Lock and Security Bit commands
  • Boot Read Protection
  • Error Correction Code (ECC)