42.7.6 Interrupt Enable Set

This register allows the user to change this register without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
Name: INTENSET
Offset: 0x09
Reset: 0x00
Property: PAC Write-Protection

Bit 76543210 
   MC1MC0VLCDIRERROVF 
Access RWRWRWRWRWRW 
Reset 000000 

Bits 4, 5 – MC Channel x Compare Match Enable

Writing a '0' to MCx has no effect.

Writing a '1' to MCx will set the corresponding Match Channel x Interrupt Disable/Enable bit, which enables the Match Channel x interrupt.

ValueDescription
0 The Match Channel x interrupt is disabled.
1 The Match Channel x interrupt is enabled.

Bit 3 – VLC Velocity Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will set the Velocity Interrupt Disable/Enable bit, which enables the Velocity interrupt.

This bit has no effect when COUNTER operation mode is selected.

ValueDescription
0 The Velocity interrupt is disabled.
1 The Velocity interrupt is enabled.

Bit 2 – DIR Direction Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will set the Direction Change Interrupt Disable/Enable bit, which enables the Direction Change interrupt.

This bit has no effect when COUNTER operation mode is selected.

ValueDescription
0 The Direction Change interrupt is disabled.
1 The Direction Change interrupt is enabled.

Bit 1 – ERR Error Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will set the Error Interrupt Disable/Enable bit, which enables the Error interrupt.

ValueDescription
0 The Error interrupt is disabled.
1 The Error interrupt is enabled.

Bit 0 – OVF Overflow/Underflow Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will set the Overflow Interrupt Disable/Enable bit, which enable the Overflow interrupt.

ValueDescription
0 The Overflow interrupt is disabled.
1 The Overflow interrupt is enabled.