5.2 Power Constraints

The following power constraints apply to the PL460 device. Deviating from these constraints may lead to unwanted device behavior.

  • PVDDAMP must be stable when transmitting. A variation of 1V above or 2V below the configured PVDDAMP voltage can damage internal regulators and must be avoided. Microchip strongly recommends monitoring the PVDDAMP voltage, and if these conditions are detected, transmissions should be disabled using the TXEN pin.
  • VDDIN and VDDIO must have the same level, 3.3V.
  • VDDPLL voltage must be derived from VDDCORE through a low-pass filter. Using a second order LC with a cutoff frequency equal to 25 kHz is recommended. The inductor can be replaced by a ferrite bead, then a cutoff frequency equal to 75 kHz could be acceptable. In those cases, it is mandatory to check the communication performances of the system to detect problems originating from poor PLL supply filtering.
Figure 5-1. Core Voltage Regulator Connectivity

Refer to the Signal Description and reference designs provided by Microchip for additional information about recommended values of decoupling capacitors and low-pass filter components.

Table 5-2. Ramp-up Slopes of PLC Amplifier Power Supplies
Parameter Min. Typ. Max. Unit
3.3V power supply ramp-up slope (Note 1, 2)0.6-24V/ms
PVDDAMP power supply ramp-up slope (Note 1, 3)1.5-16V/ms
Note:
  1. Power supply ramp-up slope recommended values take into account the recommended decoupling networks to be used on each supply rail, as well as output current capability of power supplies typically used in smart metering applications.
  2. The VDDAMP pins connected at the PCB level.
  3. The PVDDAMP pins connected at the PCB level.

For additional information on power considerations, refer to the Power On Considerations.