11.8 Power On Considerations

The Power On procedure begins by driving the ENABLE pin high to activate the embedded voltage regulator.

When the ENABLE pin is driven high, VDDCORE is activated once the ENABLE voltage reaches 1.6V.

The NRST pin must be tied to ‘0’ during power-on for a minimum of 2.5 ms after the VDDCORE is activated.

Clock signals will begin operating approximately 290 μs after the NRST pin is released. Following this, the external host CPU can access the bootloader logic to transfer the program and initiate system operation.

Figure 11-2. Power On Timing Diagram for NRST (ENABLE With Pull-Up Resistor to VDDIN)

It is recommended to apply the PVDDAMP supply at least 2.5 ms after the ENABLE pin has stabilized.

Figure 11-3. Power On Timing Diagram for PVDDAMP (ENABLE With Pull-Up Resistor to VDDIN)

If these considerations about NRST and PVDDAMP cannot be met, Microchip strongly recommends holding the NRST pin low as soon as possible at power on.