4.3.2 PIC32CX1012BZ25048 MCU Current Consumption

Table 4-4. PIC32CX1012BZ25048 MCU Current Consumption
DC Characteristics				Standard Operating Conditions: V_DD = 3.0–3.6V (Unless Otherwise Stated) Operating Temperature: -40 °C ≤ T_A ≤ +85 °C for Industrial Temperature
Param. No.	Symbol	Characteristics	Clock/Freq	Typ.	Max	Unit	Conditions
APWR_1	I_{DD_ACTIVE}^(1,2)	MCU I_DD in active mode with PMU in LDO mode	PLL 64 MHz	105	291	μA/MHz	V_DD = 3.3V
APWR_1		MCU I_DD in active mode with PMU in LDO mode	PLL 48 MHz	89	274
APWR_13		MCU I_DD in active mode with PMU in Buck mode	PLL 64 MHz	70	209
APWR_13		MCU I_DD in active mode with PMU in Buck mode	PLL 48 MHz	62	197
IPWR_1	I_{DD_IDLE}⁽³⁾	MCU I_DD in IDLE mode w/LDO mode selected	PLL 64 MHz	54	184	μA/MHz	V_DD = 3.3V
IPWR_1		MCU I_DD in IDLE mode w/LDO mode selected	PLL 48 MHz	68	249
IPWR_3		MCU I_DD in IDLE mode w/BUCK mode selected	PLL 64 MHz	77	258
IPWR_3		MCU I_DD in IDLE mode w/BUCK mode selected	PLL 48 MHz	49	178
SPWR_1	I_{DD_SLEEP}⁽⁴⁾	MCU I_DD in Sleep mode w/LDO mode selected	—	0.58	10.6	mA	XTAL OFF
SPWR_5		MCU I_DD in Sleep mode w/LDO mode selected	—	0.88	10.1	mA	XTAL ON
SPWR_29		MCU I_DD in Sleep mode w/BUCK mode selected	—	0.67	10.7	mA	XTAL ON
SPWR_33		MCU I_DD in Sleep mode w/BUCK mode selected	—	0.49	11.0	mA	XTAL OFF
BPWR_1	I_{DD_BACKUP}⁽⁵⁾	MCU I_DD in Deep Sleep mode powered from V_DDIO 3.3V	—	1.5	7.1	µA	No Back-up RAM retained
BPWR_9	I_{DD_BACKUP}⁽⁵⁾	MCU I_DD in Deep Sleep mode powered from V_DDIO 3.3V	—	1.7	11.7	µA	8 KB Back-up RAM retained
OPWR_1	I_{DD_OFF}⁽⁶⁾	MCU I_DD in OFF mode powered from V_DDIO 3.3V	—	0.36	3.99	µA	In OFF mode⁽⁷⁾, the device is entirely powered-off.
Note: 1. The test conditions are as follows: All GPIO are input and pulled up. RF System ON with default settings but not doing RF transmission. All Peripherals disabled with PMD bits. All PB clocks are divided by 16. LPRC is set as LPCLK. SOSC is disabled. PMU 1 MHz clock is derived from FRC. FRC is divided by 8. Cache is enabled and configured wait time as 0xF. WCM memories configured in Retention + NAP mode. DSU is disconnected. 2. MCU running while(1) loop with 50 NOP instructions. 3. The test conditions are as follows: All GPIO are input and pulled up. All Peripherals disabled with PMD bits. All PB clocks are divided by 16. LPRC is set as LPCLK. SOSC is disabled. PMU 1 MHz clock is derived from FRC. FRC is divided by 8. Cache is enabled and configured to wait time as 0xF. WCM memories configured in Retention + NAP mode. DSU is disconnected. RF system OFF. Entry to the Sleep mode is disabled and WFI instruction is executed. On exit by External interrupt, verified RCON status to ensure system was in the IDLE mode.
4. The test conditions SLEEP mode are as follows: All GPIO are input and pulled up. All peripherals disabled with PMD bits. All PB clocks are divided by 16. LPRC is set as LPCLK. SOSC is disabled. CLDO is configured at lowest possible voltage (VREG Trim = 0x07). PMU is configured to the Buck PSM mode on the Sleep Mode Entry. Cache is enabled and configured wait time as 0xF. WCM memories configured in Retention + NAP mode. DSU is disconnected. RF system is in low power configuration. Entry to the Sleep mode is enabled and WFI instruction is executed. On exit by External interrupt, verified RCON status to ensure system was in Sleep mode. In XTAL ON mode - PMU Buck clock is derived from POSC 16 MHz and scaled to 1 MHz. FRC is OFF. In XTAL OFF mode - PMU is clocked from FRC and XTAL 16 MHz clock is disabled and clock configuration in CRU changed to FRC. 5. The test conditions for Deep sleep mode are as follows: All GPIO are input and pulled up. All peripherals disabled with PMD bits. All PB clocks are divided by 16. LPRC is set as LPCLK. SOSC and POSC is disabled. CLDO configured at lowest possible voltage (VREG Trim = 0x07). DSU is disconnected. RF system is in low power configuration. DSWDT is enabled and configured for wake-up. Deep sleep entry is configured and WFI instruction is executed. 8 KB RAM WCM memory ON using WCMCFG.WCM1CFG[2:0]=1; WCMCFG.WCM2CFG[2:0]=1 for powered ON, RET + NAP mode. 8 KB RAM WCM memory OFF using WCMCFG.WCM1CFG[2:0]=0; WCMCFG.WCM2CFG[2:0]=0 for powered OFF.
6. The test conditions for OFF MODE are as follows: All GPIO are input and pulled up. All peripherals disabled with PMD bits. DSU is disconnected. RF system is in low power configuration. DSWDT is disabled. RTCC and POSC is disabled. Deep sleep entry is configured and WFI instruction is executed. 7. Exit OFF mode by pulling the RESET pin low or by performing a power reset. 8. Typical value measured at 25 °C and 3.3V 9. These parameters are characterized but not tested in manufacturing.