5.1.2.1 Frequency Setting

Because the phase-locked loop (PLL) ensures f_DIV= f_XTO, the fractional divider setting and the sigma delta modulator (SDM) together control the output frequency.

The frequency adjustment is done by the ffreq[17:0] control signal, which defines the fractional part of the division factor. FEMS.M[3:0] and FEMS.S[3:0] define the integer portion of the division factor. For each channel in service 0, 1 and 2, a set of data exists in the EEPROM, and the firmware copies these values into the front end registers before activating the PLL.

The RF divider and the fractional divider settings of the PLL display in the following table. Values of FEMS.M[3:0] and FEMS.S[3:0] are ambiguous and must, therefore, be calculated by using the configuration tool.

Table 5-5. RF Divider and Main Swallow Counter Setting of the Fractional-N PLL
Frequency Bands [MHz]	RF Divider Ratio	FEMS.M[3:0]	FEMS.S[3:0]	FECR.LBNHB	FECR.S4N3
310.00-318.00	6	6	0;1;2;3	1	0
418.00-477.00	4	8;9	0;1;2; … ;(M-3)	1	1
836.00-956.00	2	8;9	0;1;2; … ;(M-3)	0	0

The fractional-N PLL output frequency, f_out = f_LO as a function of the settings, can be calculated with:

f_{O U T} = f_{X T O} \times (\frac{f f r e q + 0.5}{2^{17 + L B N H B}} + M \times 2^{2 - L B N H B} + S \times 2^{- (1 + L B N H B)}) (59)

ffreq as a function of frequency and other settings can be calculated with:

f_{f r e q} = (\frac{f_{O U T}}{f_{X T O}} - M \times 2^{2 - L B N H B} - S \times 2^{- (1 + L B N H B)}) \times 2^{(17 + L B N H B)} - 0.5 (60)

using:

ffreq = ffreq[17:0] = {16384,16385,…, 180224}

LBNHB = FECR.LBNHB = {0, 1}, 1 – Low-band (315 MHz, 433 MHz), 0 – High-band (868 MHz, 915 MHz)

f_XTO= {23.800,…., 26.200} MHz; PLL reference frequency

M = FEMS.M[3:0] = {2, 3, … , 15};

S = FEMS.S[3:0] = {0, 1, …, M-3};

The FFREQ values, which are stored in the EEPROM, correspond to the receive mode and represent the center receive frequency minus the intermediate frequency (approximately 251 kHz).