50.4.17 SPI Mode Requirements

Table 50-22. SPI HOST MODE
Standard Operating Conditions (unless otherwise stated)
Param No.Sym.CharacteristicMin.Typ. †Max.UnitsConditions
SP69*TSCKSCK Cycle Time (2x Prescaled)61.0——nsTransmit mode only
—16(1)—MHz
95.0——nsFull-Duplex mode
—10(1)—MHz
SP70*

TSSL2SCH,

TSSL2SCL

SDO to SCK↓ or SCK↑ inputTSCK——nsFST = 0
SP70A*0——nsFST = 1
SP71*TSCHSCK output high time 0.5 TSCK - 12 —0.5 TSCK + 12 ns
SP72*TSCLSCK output low time0.5 TSCK - 12 —0.5 TSCK + 12 ns
SP73*

TDIV2SCH,

TDIV2SCL

Setup time of SDI data input to SCK edge85.0——ns
SP74*

TSCH2DIL,

TSCL2DIL

Hold time of SDI data input to SCK edge0——ns
SP74A*Hold time of SDI data input to final SCK0.5 TSCKnsCKE = 0,

SMP = 1

SP75*TDORSDO data output rise time—10.025.0nsCL = 50 pF
SP76*TDOFSDO data output fall time—10.025.0nsCL = 50 pF
SP78*TSCRSCK output rise time—10.025.0nsCL = 50 pF
SP79*TSCFSCK output fall time—10.025.0nsCL = 50 pF
SP80*

TSCH2DOV,

TSCL2DOV

SDO data output valid after SCK edge-15.0—15.0nsCL = 50 pF
SP81*

TDOV2SCH,

TDOV2SCL

SDO data output valid to first SCK edgeTSCK - 10——ns

CL = 50 pF

CKE = 1

SP82*TSSL2DOVSDO data output valid after SS↓ edge——50.0nsCL = 20 pF
SP83*

TSCH2SSH,

TSCL2SSH

SS ↑ after last SCK edgeTSCK - 10——ns
SP84*

TSSH2SSL

SS ↑ to SS↓ edgeTSCK - 10——ns

* These parameters are characterized but not tested.

† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.

Note:
  1. SMP bit in the SPIxCON1 register must be set and the slew rate control must be disabled on the clock and data pins (clear the corresponding bits in SLRCONx register) for SPI to operate over 4 MHz.
Table 50-23. SPI CLIENT MODE
Standard Operating Conditions (unless otherwise stated)
Param No.Sym.CharacteristicMin.Typ. †Max.UnitsConditions
SP69*TSCKSCK Total Cycle Time47.0——nsReceive mode only
—20(1)—MHz
95.0——nsFull-Duplex mode
—10(1)—MHz
SP70*

TSSL2SCH,

TSSL2SCL

SS↓ to SCK↓ or SCK↑ input0——nsCKE = 0
25.0——nsCKE = 1
SP71*TSCHSCK input high time20.0——ns
SP72*TSCLSCK input low time20.0——ns
SP73*

TDIV2SCH,

TDIV2SCL

Setup time of SDI data input to SCK edge10.0——ns
SP74*

TSCH2DIL,

TSCL2DIL

Hold time of SDI data input to SCK edge0——ns
SP75*TDORSDO data output rise time———ns
SP76*TDOFSDO data output fall time———ns
SP77*TSSH2DOZSS↑ to SDO output high-impedance———ns
SP80*

TSCH2DOV,

TSCL2DOV

SDO data output valid after SCK edge———ns
SP82*TSSL2DOVSDO data output valid after SS↓ edge———ns
SP83*

TSCH2SSH,

TSCL2SSH

SS ↑ after SCK edge20.0——ns
SP84*

TSSH2SSL

SS ↑ to SS↓ edge47.0——ns

* These parameters are characterized but not tested.

† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.

Note:
  1. SMP bit in the SPIxCON1 register must be set and the slew rate control must be disabled on the clock and data pins (clear the corresponding bits in SLRCONx register) for SPI to operate over 4 MHz.
Figure 50-13. SPI Host Mode Timing (CKE = 0, SMP = 0)
Note: Refer to Figure 50-3 for more details.
Figure 50-14. SPI Host Mode Timing (CKE = 1, SMP = 1)
Note: Refer to Figure 50-3 for more details.
Figure 50-15. SPI Client Mode Timing (CKE = 0)
Note: Refer to Figure 50-3 for more details.
Figure 50-16. SPI Client Mode Timing (CKE = 1)
Note: Refer to Figure 50-3 for more details.