36.6.7 Sleep Mode Operation
The ONDEMAND and RUNSTDBY bits in the Control A register (CTRLA) control the behavior of the ADC during Standby Sleep mode, in cases where the ADC is enabled (CTRLA.ENABLE = 1). When exiting Standby Sleep mode the software trigger bit in the Synchronization Busy register (SYNCBUSY.SWTRIG) will be '1'. After the next RESULT, start the ADC again by writing the Software Trigger Start bit (SWTRIG.START) to '1'. For further details on available options, refer to the following table.
When the device is in Standby Sleep mode, the DMA is not able to write the SWTRIG register. To write the SWTRIG register with the DMA the device must be in Active mode or in Idle Sleep mode.
Note: When CTRLA.ONDEMAND = 1, the analog block
is powered off when the conversion is complete. When a start request is detected, the
system returns from sleep and starts a new conversion after the start-up time delay.
| CTRLA.RUNSTDBY | CTRLA.ONDEMAND | CTRLA.ENABLE | Description |
|---|---|---|---|
| x | x | 0 | Disabled |
| 0 | 0 | 1 | Run in all sleep modes except Standby mode. |
| 0 | 1 | 1 | Run in all sleep modes on request, except Standby mode. |
| 1 | 0 | 1 | Run in all sleep modes. |
| 1 | 1 | 1 | Run in all sleep modes on request. |