29.6.1 Principle of Operation

The basic structure of the SERCOM serial engine is shown in Figure 29-2. Labels in capital letters are synchronous to the system clock and accessible by the CPU; labels in lowercase letters can be configured to run on the GCLK_SERCOMx_CORE clock or an external clock.

The transmitter consists of a single write buffer and a shift register.

The receiver consists of a one-level (I²C), two-level (USART, SPI) receive buffer and a shift register.

The baud-rate generator is capable of running on the GCLK_SERCOMx_CORE clock or an external clock.

Address matching logic is included for SPI and I²C operation.