20.9 Intellectual Property Protection

Intellectual property protection consists of restricting access to internal memories from external tools when the device is protected, and this is accomplished by setting the NVMCTRL security bit. This protected state can be removed by issuing a Chip-Erase (refer to Chip Erase), as long as the Set Chip Erase Hard Lock (SCEHL) command has not been issued in the NVMCTRL. Once the SCEHL command has been issued, STATUS2:CEHL will be set and it becomes permanently impossible to perform a Chip-Erase, and therefore permanently impossible to remove the protected state. When the device is protected, read/write accesses using the AHB-AP are limited to the DSU address range and DSU commands are restricted. When issuing a Chip-Erase, sensitive information is erased from volatile memory and Flash.

The DSU implements a security filter that monitors the AHB transactions inside the DAP. If the device is protected, then AHB-AP read/write accesses outside the DSU external address range are discarded, causing an error response that sets the Arm AHB-AP sticky error bits (refer to the Arm Debug Interface v5 Architecture Specification on www.arm.com).

The DSU can be accessed using any one of these options:
  • Internally from the CPU, without any limitation, even when the device is protected
  • Externally from a debug adapter, with some restrictions when the device is protected
For security reasons, DSU features have limitations when used from a debug adapter. To differentiate external accesses from internal ones, the first 0x100 bytes of the DSU register map has been mirrored at offset 0x100:
  • The first 0x100 bytes form the internal address range
  • The next 0x100 bytes form the external address range

When the device is protected, the DAP can only issue MEM-AP accesses in the DSU range 0x0100-0x1FFF.

The DSU operating registers are located in the 0x0000-0x00FF area and remapped in 0x0100-0x01FF to differentiate accesses coming from a debugger and the CPU. If the device is protected and an access is issued in the region 0x0100-0x01FF, it is subject to security restrictions. For more information, refer to the Table 20-1.

Figure 20-4. APB Memory Mapping

Some features not activated by APB transactions are not available when the device is protected:

Table 20-1. Feature Availability Under Protection
Features Availability when the device is protected
CPU Reset Extension Yes
Clear CPU Reset Extension No
Debugger Cold-Plugging Yes
Debugger Hot-Plugging No