20.7 Chip Erase

Chip Erase consists of removing all sensitive information stored in the chip and clearing the NVMCTRL security bit. Therefore, all volatile memories and the Flash memory Main array and Data Flash section will be erased. The Flash auxiliary rows, including the user row, will not be erased.

Chip Erase is only possible as long as the Set Chip Erase Hard Lock (SCEHL) command has not been issued in the NVMCTRL.

When the device is protected, the debugger must first reset the device in order to be detected. This ensures that internal registers are reset after the protected state is removed. The Chip Erase operation is triggered by writing a '1' to the Chip Erase bit in the Control register (CTRL.CE). This command will be discarded if the DSU is protected by the Peripheral Access Controller (PAC). Once issued, the module clears volatile memories prior to erasing the Flash array. To ensure that the Chip Erase operation is completed, check the Done bit of the Status A register (STATUSA.DONE).

The Chip Erase operation depends on clocks and power management features that can be altered by the CPU. For that reason, it is recommended to issue a Chip Erase after a Cold Plugging procedure to ensure that the device is in a known and safe state.