14.6.5 Digital Phase-Locked Loop (FDPLL96M) Operation

The task of the DPLL is to maintain coherence between the input (reference) signal and the respective output frequency, CLK_DPLL through phase comparison. The DPLL controller supports three independent sources of reference clocks:

  • XOSC32K: This clock is provided by the 32.768 kHz External Crystal Oscillator (XOSC32K).
  • XOSC: This clock is provided by the External Multipurpose Crystal Oscillator (XOSC).
  • GCLK: This clock is provided by the Generic Clock Controller.

When the controller is enabled, the relationship between the reference clock frequency and the output clock frequency is calculated as below:

f CK = f CKR × ( LDR + 1 + LDRFRAC 16 ) × 1 2 PRESC

Where, fCK is the frequency of the DPLL output clock, LDR is the loop divider ratio integer part, LDRFRAC is the loop divider ratio fractional part, fCKR is the frequency of the selected reference clock, and PRESC is the output prescaler value.

Figure 14-2. DPLL Block Diagram

When the controller is disabled, the output clock is low. If the Loop Divider Ratio Fractional part bit field in the DPLL Ratio register (DPLLRATIO.LDRFRAC) is zero, the DPLL works in integer mode. Otherwise, the fractional mode is activated. The fractional part has a negative impact on the jitter of the DPLL.

For example (integer mode only), assuming FCKR = 32 kHz and FCK = 48 MHz, the multiplication ratio is 1500. It means that LDR shall be set to 1499.

For example (fractional mode), assuming FCKR = 32 kHz and FCK = 48.006 MHz, the multiplication ratio is 1500.1875 (1500 + 3/16). Thus LDR is set to 1499 and LDRFRAC to 3.