14.6.4 48 MHz Internal Oscillator (OSC48M) Operation
The OSC48M is an internal oscillator operating in open-loop mode and generating 48 MHz frequency. The OSC48M frequency is selected by writing to the Division Factor field in the OSC48MDIV register (OSC48MDIV.DIV). OSC48M is enabled by writing '1' to the Oscillator Enable bit in the OSC48M Control register (OSC48MCTRL.ENABLE), and disabled by writing a '0' to this bit.
After enabling OSC48M, the OSC48M clock is output as soon as the oscillator is ready (STATUS.OSC48MRDY = 1). User must ensure that the OSC48M is disabled before enabling it by reading STATUS.OSC48MRDY = 0.
After reset, OSC48M is enabled and serves as the default clock source at 4MHz.
OSC48M will behave differently in different sleep modes based on the settings of OSC48MCTRL.RUNSTDBY, OSC48MCTRL.ONDEMAND, and OSC48MCTRL.ENABLE. If OSC48MCTRL.ENABLE = 0, the OSC48M will be always stopped. For OSC48MCTRL.ENABLE = 1, the table below is valid:
| CPU Mode | OSC48MCTRL.RUNSTDBY | OSC48MCTRL.ONDEMAND | Sleep Behavior |
|---|---|---|---|
| Active or Idle | - | 0 | Always run |
| Active or Idle | - | 1 | Run if requested by peripheral |
| Standby | 1 | 0 | Always run |
| Standby | 1 | 1 | Run if requested by peripheral |
| Standby | 0 | - | Run if requested by peripheral |
After a hard reset, or when waking up from a Sleep mode where the OSC48M was disabled, the OSC48M will need time to stabilize on the correct frequency (refer to 43 Electrical Characteristics 85℃). This start-up time can be configured by changing the Oscillator Start-Up Delay bit group (OSC48MSTUP.STARTUP) in the OSC48M Startup register. During the start-up time, the oscillator output is masked to ensure that no unstable clock propagates to the digital logic. The OSC48M Ready bit in the Status register (STATUS.OSC48MRDY) is set when the oscillator is stable and ready to be used as a clock source. An interrupt is generated on a zero-to-one transition on STATUS.OSC48MRDY if the OSC48M Ready bit in the Interrupt Enable Set register (INTENSET.OSC48MRDY) is set.
Faster start-up times are achievable by selecting shorter delays. However, the oscillator frequency may not stabilize within tolerances when short delays are used. If a fast start-up time is desired at the expense of initial accuracy, the division factor should be set to two or higher (OSC48MDIV.DIV > 0).
The OSC48M is used as a clock source for the generic clock generators. The OSC48M supports the change of frequency while running with a write to the OSC48M Divider register (OSC48MDIV.DIV). The OSC48M must be running and the OSC48M on demand bit (OSC48MCTRL.ONDEMAND) must be cleared when the OSC48MDIV.DIV is changed, to ensure synchronization is complete. The OSC48M must remain enabled until the sync busy flag returns to '0' (OSC48MSYNCBUSY.OSC48MDIV = 0).