26.2 Features

• 32-bit AHB interface for reads and writes
• Data Flash
• All NVM sections are memory mapped to the AHB, including calibration and system configuration
• 32-bit APB interface for commands and control
• Programmable wait states
• 16 regions can be individually protected or unprotected against erase and writes
• Additional protection for bootloader against erase and writes
• Supports device protection through a security bit
• Supports permanent disabling of the Chip-Erase feature
• Interface to Power Manager for power-down of Flash blocks in sleep modes
• Can optionally wake up on exit from sleep or on first access
• Direct-mapped cache for the main array and the Data Flash section