12.4 Signal Description

Table 12-1. GCLK Signal Description
Signal Name Type Description
GCLK_IO[7:0](1,2,3) Digital I/O

Clock source for Generators when input

Generic Clock signal when output
Note:
  1. One signal can be mapped on several pins.
  2. Each GCLK_IO[x] signal is connected to the related Generic Clock Generator x, for x in [7:0].
  3. There is no GCLK_IO8 input or output for the Generic Clock Generator 8.