37.6.7 Sleep Mode Operation
The ONDEMAND and RUNSTDBY bits in the Control A register (CTRLA) control the behavior of the SDADC during Standby Sleep mode, in cases where the SDADC is enabled (CTRLA.ENABLE = 1). When CTRLA.ONDEMAND is one, the analog block is powered-off when the conversion is complete. When a start request is detected, the system returns from sleep and starts a new conversion after the start-up time delay.
| CTRLA.RUNSTDBY | CTRLA.ONDEMAND | CTRLA.ENABLE | Description |
|---|---|---|---|
| x | x | 0 | Disabled |
| 0 | 0 | 1 | Run in all sleep modes except Standby mode. |
| 0 | 1 | 1 | Run in all sleep modes on request, except Standby mode. |
| 1 | 0 | 1 | Run in all sleep modes. |
| 1 | 1 | 1 | Run in all sleep modes on request. |
When the device is in STANDBY sleep mode the DMA is not able to write the SWTRIG register. To write the SWTRIG register with the DMA the device must be in Active mode or IDLE sleep mode.