14.9.2 WDTCSR – Watchdog Timer Control Register

Name: WDTCSR
Offset: 0x60
Reset: 0x00

Bit 76543210 
 WDIFWDIEWDP[3]WDCEWDEWDP[2:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bit 7 – WDIF Watchdog Interrupt Flag

This bit is set when a time out occurs in the Watchdog Timer and the Watchdog Timer is configured for interrupt. WDIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, WDIF is cleared by writing a '1' to it. When the I-bit in SREG and WDIE are set, the Watchdog Timeout Interrupt is executed.

Bit 6 – WDIE Watchdog Interrupt Enable

When this bit is written to '1' and the I-bit in the Status register is set, the Watchdog Interrupt is enabled. If WDE is cleared in combination with this setting, the Watchdog Timer is in Interrupt mode, and the corresponding interrupt is executed if timeout in the Watchdog Timer occurs. If WDE is set, the Watchdog Timer is in Interrupt and System Reset mode. The first timeout in the Watchdog Timer will set WDIF. Executing the corresponding interrupt vector will clear WDIE and WDIF automatically by hardware (the Watchdog goes to System Reset mode).

This is useful for keeping the Watchdog Timer security while using the interrupt. To stay in Interrupt and System Reset mode, WDIE must be set after each interrupt. This should not be done within the interrupt service routine itself, as this might compromise the safety function of the Watchdog System Reset mode. If the interrupt is not executed before the next timeout, a System Reset will be applied.

Table 14-1. Watchdog Timer Configuration
WDTON(1)WDEWDIEModeAction on Time-out
100StoppedNone
101Interrupt modeInterrupt
110System Reset modeReset
111Interrupt and System Reset modeInterrupt, then go to System Reset mode
0xxSystem Reset modeReset
Note: 1. WDTON Fuse set to '0' means programmed and '1' means unprogrammed.

Bit 5 – WDP[3] Watchdog Timer Prescaler 3

Bit 4 – WDCE Watchdog Change Enable

This bit is used in timed sequences for changing WDE and prescaler bits. To clear the WDE bit, and/or change the prescaler bits, WDCE must be set. Once written to '1', hardware will clear WDCE after four clock cycles. Refer to Overview in section Watchdog Timer for information on how to use WDCE.

Bit 3 – WDE Watchdog System Reset Enable

WDE is overridden by WDRF in MCUSR. This means that WDE is always set when WDRF is set. To clear WDE, WDRF must be cleared first. This feature ensures multiple resets during conditions causing failure, and a safe start-up after the failure.

Bits 2:0 – WDP[2:0] Watchdog Timer Prescaler 2, 1, and 0

The WDP[3:0] bits determine the Watchdog Timer prescaling when the Watchdog Timer is running. The different prescaling values and their corresponding time out periods are shown in the following table.

Table 14-2. Watchdog Timer Prescale Select
WDP[3]WDP[2]WDP[1]WDP[0]Number of WDT Oscillator (Cycles)Oscillator
00002K (2048)16 ms
00014K (4096)32 ms
00108K (8192)64 ms
001116K (16384)0.125s
010032K (32768)0.25s
010164K (65536)0.5s
0110128K (131072)1.0s
0111256K (262144)2.0s
1000512K (524288)4.0s
10011024K (1048576)8.0s
1010Reserved
1011
1100
1101
1110
1111