23.5.1 SPI Control Register 0
When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
The device is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in Opcode for the IN and OUT instructions. For the extended I/O space from 0x60 in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
| Name: | SPCR0 |
| Offset: | 0x4C |
| Reset: | 0x00 |
| Property: | When addressing as I/O register: address offset is 0x2C |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SPIE0 | SPE0 | DORD0 | MSTR0 | CPOL0 | CPHA0 | SPR0 [1:0] | |||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 7 – SPIE0 SPI0 Interrupt Enable
This bit causes the SPI interrupt to be executed if the SPIF bit in the SPSR register is set and if the global interrupt enable bit in SREG is set.
Bit 6 – SPE0 SPI0 Enable
When the SPE bit is written to one, the SPI is enabled. This bit must be set to enable any SPI operations.
Bit 5 – DORD0 Data0 Order
When the DORD bit is written to one, the LSB of the data word is transmitted first.
When the DORD bit is written to zero, the MSB of the data word is transmitted first.
Bit 4 – MSTR0 Master/Slave0 Select
This bit selects the Master SPI mode when written to one, and the Slave SPI mode when written logic zero. If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable Master SPI mode.
Bit 3 – CPOL0 Clock0 Polarity
When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low when idle. Refer to Figure 23-3 and Figure 23-4 for an example. The CPOL functionality is summarized below:
| CPOL0 | Leading Edge | Trailing Edge |
|---|---|---|
| 0 | Rising | Falling |
| 1 | Falling | Rising |
Bit 2 – CPHA0 Clock0 Phase
The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading (first) or trailing (last) edge of SCK. Refer to Figure 23-3 and Figure 23-4 for an example. The CPHA functionality is summarized below:
| CPHA0 | Leading Edge | Trailing Edge |
|---|---|---|
| 0 | Sample | Setup |
| 1 | Setup | Sample |
Bits 1:0 – SPR0 [1:0] SPI0 Clock Rate Select
These two bits control the SCK rate of the device configured as a master. SPR1 and SPR0 have no effect on the slave. The relationship between SCK and the Oscillator Clock frequency fosc is shown in the table below.
| SPI2X | SPR0[1] | SPR0[0] | SCK Frequency |
|---|---|---|---|
| 0 | 0 | 0 | fosc/4 |
| 0 | 0 | 1 | fosc/16 |
| 0 | 1 | 0 | fosc/64 |
| 0 | 1 | 1 | fosc/128 |
| 1 | 0 | 0 | fosc/2 |
| 1 | 0 | 1 | fosc/8 |
| 1 | 1 | 0 | fosc/32 |
| 1 | 1 | 1 | fosc/64 |