12.5.1 XOSC Failure Detection Control And Status Register
| Name: | XFDCSR |
| Offset: | 0x62 |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| XFDIF | XFDIE | ||||||||
| Access | R | R/W | |||||||
| Reset | 0 | 0 |
Bit 1 – XFDIF Failure Detection Interrupt Flag
This bit is set when a failure is detected, and it can be cleared only by reset.
It serves as a status bit for CFD.
Note: This bit is
read-only.
Bit 0 – XFDIE Failure Detection Interrupt Enable
Setting this bit will enable the interrupt which will be issued when XFDIF is set. This bit is enable only. Once enabled, it is not possible for the user to disable.