25.3 Clock Generation

The Clock Generation logic generates the base clock for the Transmitter and Receiver. For USART MSPIM mode of operation only internal clock generation (i.e. master operation) is supported. The Data Direction Register for the XCKn pin (DDR_XCKn) must therefore be set to one (i.e. as output) for the USART in MSPIM to operate correctly. Preferably the DDR_XCKn should be set up before the USART in MSPIM is enabled (i.e. TXENn and RXENn bit set to one).

The internal clock generation used in MSPIM mode is identical to the USART synchronous master mode. The table below contains the equations for calculating the baud rate or UBRRn setting for Synchronous Master Mode.

Table 25-1. Equations for Calculating Baud Rate Register Setting
Operating Mode	Equation for Calculating Baud Rate⁽¹⁾	Equation for Calculating UBRRn Value
Synchronous Master mode	$BAUD = \frac{f_{OSC}}{2 (U B R R n + 1)}$	$U B R R n = \frac{f_{OSC}}{2 BAUD} - 1$

Note: 1. The baud rate is defined to be the transfer rate in bit per second (bps)


BAUD	Baud rate (in bits per second, bps)
f_OSC	System Oscillator clock frequency
UBRRn	Contents of the UBRRnH and UBRRnL Registers, (0-4095)

ATmega328PB

25.3 Clock Generation