18.4.1 Analog Comparator Control and Status Register

Name: ACSRA
Offset: 0x1F
Reset: 0

Bit 76543210 
 ACDACBGACOACIACIEACICACISn[1:0] 
Access R/WR/WRR/WR/WR/WR/WR/W 
Reset 00000000 

Bit 7 – ACD Analog Comparator Disable

When this bit is written logic one, the power to the Analog Comparator is switched off. This bit can be set at any time to turn off the Analog Comparator. This will reduce power consumption in Active and Idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed.

Bit 6 – ACBG Analog Comparator Bandgap ENABLE

When this bit is set, 1.1V bandgap reference voltage is enabled. When ACPMUX bit is also set, bandgap reference voltage is applied to the positive input of analog comparator. It is advised that bandgap reference is first enabled by writing one to ACBG bit and then selected by writing one to ACPMUX bit to allow the stabilization of voltage.

Bit 5 – ACO Analog Comparator Output

The output of the Analog Comparator is synchronized and then directly connected to ACO. The synchronization introduces a delay of 1 - 2 clock cycles.

Bit 4 – ACI Analog Comparator Interrupt Flag

This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.

Bit 3 – ACIE Analog Comparator Interrupt Enable

When the ACIE bit is written logic one and the I-bit in the Status Register is set, the Analog Comparator interrupt is activated. When written logic zero, the interrupt is disabled.

Bit 2 – ACIC Analog Comparator Input Capture Enable

When written logic one, this bit enables the input capture function in Timer/Counter0 to be triggered by the Analog Comparator. The comparator output is in this case directly connected to the input capture front-end logic, making the comparator utilize the noise canceler and edge select features of the Timer/Counter0 Input Capture interrupt. When written logic zero, no connection between the Analog Comparator and the input capture function exists. To make the comparator trigger the Timer/Counter0 Input Capture interrupt, the ICIE1 bit in the Timer Interrupt Mask Register (TIMSK0) must be set.

Bits 1:0 – ACISn[1:0] Analog Comparator Interrupt Mode Select [n = 1:0]

These bits determine which comparator events that trigger the Analog Comparator interrupt.

Table 18-1. ACIS[1:0] Settings
ACIS1ACIS0Interrupt Mode
00Comparator Interrupt on Output Toggle.
01Reserved
10Comparator Interrupt on Falling Output Edge.
11Comparator Interrupt on Rising Output Edge.

When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by clearing its Interrupt Enable bit in the ACSR Register. Otherwise an interrupt can occur when the bits are changed.