10.7.1 Clock Main Settings Register
| Name: | CLKMSR |
| Offset: | 0x37 |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CLKMS[1:0] | |||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 | |||||||
Bits 1:0 – CLKMS[1:0] Clock Main Select Bits
These bits select the main clock source of the system. The bits can
be written at run-time to switch the source of the main clock. The clock system
ensures glitch free switching of the main clock source.
| CLKM | Main Clock Source |
|---|---|
| 00 | Calibrated Internal 8MHz Oscillator |
| 01 | Internal 128kHz Oscillator (WDT Oscillator) |
| 10 | External clock |
| 11 | Reserved |
To avoid unintentional switching of main clock source, a protected change
sequence must be followed to change the CLKMS bits, as follows:
- Write the signature for change enable of protected I/O register to register CCP.
- Within four instruction cycles, write the CLKMS bits with the desired value.