10.7.3 Clock Prescaler Register

Name: CLKPSR
Offset: 0x36
Reset: 0x00000011
Property: -

Bit 76543210 
     CLKPS[3:0] 
Access R/WR/WR/WR/W 
Reset 0011 

Bits 3:0 – CLKPS[3:0] Clock Prescaler Select

These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used. The division factors are given in the table below.

Table 10-6. Clock Prescaler Select
CLKPS[3:0]Clock Division Factor
00001
00012
00104
00118 (default)
010016
010132
011064
0111128
1000256
1001Reserved
1010Reserved
1011Reserved
1100Reserved
1101Reserved
1110Reserved
1111Reserved
To avoid unintentional changes of clock frequency, a protected change sequence must be followed to change the CLKPS bits:
  1. Write the signature for change enable of protected I/O register to register CCP
  2. Within four instruction cycles, write the desired value to CLKPS bits

At start-up, CLKPS bits are reset to 0b0011 to select the clock division factor of 8. If the selected clock source has a frequency higher than the maximum allowed the application software must make sure a sufficient division factor is used. To make sure the write procedure is not interrupted, interrupts must be disabled when changing prescaler settings.