19.6 Prescaling and Conversion Timing

By default, the successive approximation circuitry requires an input clock frequency between 50 kHz and 200 kHz to get maximum resolution.

The ADC module contains a prescaler, which generates an acceptable ADC clock frequency from any CPU frequency above 100 kHz. The prescaling is selected by the ADC Prescaler Select bits in the ADC Control and Status Register A (ADCSRA.ADPS). The prescaler starts counting from the moment the ADC is switched on by writing the ADC Enable bit ADCSRA.ADEN to '1'. The prescaler keeps running for as long as ADEN=1, and is continuously reset when ADEN=0.

Figure 19-3. ADC Prescaler

When initiating a single ended conversion by writing a '1' to the ADC Start Conversion bit (ADCSRA.ADSC), the conversion starts at the following rising edge of the ADC clock cycle.

A normal conversion takes 15 ADC clock cycles. The first conversion after the ADC is switched on (i.e., ADCSRA.ADEN is written to '1') takes 26 ADC clock cycles in order to initialize the analog circuitry, as the figure below.

Figure 19-4. ADC Timing Diagram, First Conversion (Single Conversion Mode)

The actual sample-and-hold takes place 4 ADC clock cycles after the start of a normal conversion and 15 ADC clock cycles after the start of an first conversion. When a conversion is complete, the result is written to the ADC Data Registers (ADCL), and the ADC Interrupt Flag (ADCSRA.ADIF) is set. In Single Conversion mode, ADCSRA.ADSC is cleared simultaneously. The software may then set ADCSRA.ADSC again, and a new conversion will be initiated on the first rising ADC clock edge.

Figure 19-5. ADC Timing Diagram, Single Conversion

When Auto Triggering is used, the prescaler is reset when the trigger event occurs, as the next figure. This assures a fixed delay from the trigger event to the start of conversion. In this mode, the sample-and-hold takes place 4.5 ADC clock cycles after the rising edge on the trigger source signal. Two additional CPU clock cycles are used for synchronization logic.

Figure 19-6. ADC Timing Diagram, Auto Triggered Conversion

In Free Running mode, a new conversion will be started immediately after the conversion completes, while ADCRSA.ADSC remains high. See also the ADC Conversion Time table below.

Figure 19-7. ADC Timing Diagram, Free Running Conversion
Table 19-1. ADC Conversion Time
ConditionSample & Hold 
(Cycles from Start of Conversion)Conversion Time 
(Cycles)
First conversion(1)1526
Normal conversions415
Auto Triggered conversions4.515.5
Free Running conversion415
Note:
  1. When gain amplifier is active, also includes the first conversion after a change in channel, reference or gain setting.