12.6.2 VCC Level Monitoring Control and Status register
| Name: | VLMCSR |
| Offset: | 0x34 |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| VLMF | VLMIE | VLM[2:0] | |||||||
| Access | R | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
Bit 7 – VLMF VLM Flag
This bit is set by the VLM circuit to indicate that a voltage level condition has been triggered. The bit is cleared when the trigger level selection is set to “Disabled”, or when voltage at VCC rises above the selected trigger level.
Bit 6 – VLMIE VLM Interrupt Enable
Bits 2:0 – VLM[2:0] Trigger Level of Voltage Level Monitor
These bits set the trigger level for the voltage level monitor.
| VLM[2:0] | Label | Description |
|---|---|---|
| 000 | VLM0 | Voltage Level Monitor disabled |
| 001 | VLM1L |
Triggering generates a regular Power-On Reset (POR). The VLM flag is not set |
| 010 | VLM1H | |
| 011 | VLM2 | Triggering sets the VLM Flag (VLMF) and generates a VLM interrupt, if enabled |
| 100 | VLM3 | |
| 101 | Not allowed | |
| 110 | Not allowed | |
| 111 | Not allowed | |