11.6.1 Sleep Mode Control Register

The Sleep Mode Control Register contains control bits for power management.

Name: SMCR
Offset: 0x3A
Reset: 0x00

Bit 76543210 
     SM[2:0]SE 
Access R/WR/WR/WR/W 
Reset 0000 

Bits 3:1 – SM[2:0] Sleep Mode Select

The SM[2:0] bits select between the five available sleep modes.

Table 11-2. Sleep Mode Select
SM[2:0]Sleep Mode
000Idle
001ADC Noise Reduction
010Power-down
011Reserved
100Standby
101Reserved
110Reserved
111Reserved

Bit 0 – SE Sleep Enable

The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer’s purpose, it is recommended to write the Sleep Enable (SE) bit to one just before the execution of the SLEEP instruction and to clear it immediately after waking up.