28.1 Rev D - 10/2016 AVR CPU Core:New section added, Accessing 16-bit Registers.Stack Pointer (SPL and SPH) register updated.USART - Universal Synchronous Asynchronous Receiver Transceiver: Added UCSR0D.SFDE bit and corrected RXIE bit name to RXSIE.Updated presentation of the UBRR0L and UBRR0H registers.TC0 - 16-bit Timer/Counter0 with PWM:Updated presentation of theTCNT0L and TCNT0H, OCR0AL and OCR0AH, and ICR0L and ICR0H registers.ADC - Analog to Digital Converter:Updated the ADCL and ADCH registers (for both ADLAR=0 and 1).
