49.7.18 TC QDEC Interrupt Disable Register

Name: TC_QIDR
Offset: 0xCC
Reset: 
Property: Write-only

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
     MPEQERRDIRCHGIDX 
Access WWWW 
Reset  

Bit 3 – MPE Consecutive Missing Pulse Error

ValueDescription
0 No effect.
1 Disables the interrupt when an occurrence of MAXCMP consecutive missing pulses has been detected.

Bit 2 – QERR Quadrature Error

ValueDescription
0 No effect.
1 Disables the interrupt when a quadrature error occurs on PHA, PHB.

Bit 1 – DIRCHG Direction Change

ValueDescription
0 No effect.
1 Disables the interrupt when a change on rotation direction is detected.

Bit 0 – IDX Index

ValueDescription
0 No effect.
1 Disables the interrupt when a rising edge occurs on IDX input.