49.7.18 TC QDEC Interrupt Disable Register
| Name: | TC_QIDR |
| Offset: | 0xCC |
| Reset: | – |
| Property: | Write-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| MPE | QERR | DIRCHG | IDX | ||||||
| Access | W | W | W | W | |||||
| Reset | – | – | – | – |
Bit 3 – MPE Consecutive Missing Pulse Error
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Disables the interrupt when an occurrence of MAXCMP consecutive missing pulses has been detected. |
Bit 2 – QERR Quadrature Error
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Disables the interrupt when a quadrature error occurs on PHA, PHB. |
Bit 1 – DIRCHG Direction Change
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Disables the interrupt when a change on rotation direction is detected. |
Bit 0 – IDX Index
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Disables the interrupt when a rising edge occurs on IDX input. |