34.9.6 Coding Timing Parameters
All timing parameters are defined for one chip select and are grouped together in one register according to their type.
The SMC_SETUP register groups the definition of all setup parameters:
- NRD_SETUP
- NCS_RD_SETUP
- NWE_SETUP
- NCS_WR_SETUP
The SMC_PULSE register groups the definition of all pulse parameters:
- NRD_PULSE
- NCS_RD_PULSE
- NWE_PULSE
- NCS_WR_PULSE
The SMC_CYCLE register groups the definition of all cycle parameters:
- NRD_CYCLE
- NWE_CYCLE
The following table shows how the timing parameters are coded and their permitted range.
| Coded Value | Number of Bits | Effective Value | Permitted Range | |
|---|---|---|---|---|
| Coded Value | Effective Value | |||
| setup [5:0] | 6 | 128 × setup[5] + setup[4:0] | 0 ≤ 31 | 0 ≤ 128+31 |
| pulse [6:0] | 7 | 256 × pulse[6] + pulse[5:0] | 0 ≤ 63 | 0 ≤ 256+63 |
| cycle [8:0] | 9 | 256 × cycle[8:7] + cycle[6:0] | 0 ≤ 127 | 0 ≤ 256+127 0 ≤ 512+127 0 ≤ 768+127 |