Read the XDMAC_GS register to choose a free channel.
Clear the pending Interrupt Status bit by reading the chosen XDMAC_CISx register.
Build a linked list of transfer descriptors in memory. The descriptor view is programmable on a per descriptor basis. The linked list items structure must be word aligned. MBR_UBC.NDE must be configured to 0 in the last descriptor to terminate the list.
Configure field NDA in the XDMAC Channel x Next Descriptor
Address Register (XDMAC_CNDAx) with the first descriptor address and bit
XDMAC_CNDAx.NDAIF with the Host interface identifier.
Configure the XDMAC_CNDCx register:
Set XDMAC_CNDCx.NDE to enable the descriptor fetch.
Set XDMAC_CNDCx.NDSUP to update the source address at the descriptor fetch time,
otherwise clear this bit.
Set XDMAC_CNDCx.NDDUP to update the destination address at the descriptor fetch
time, otherwise clear this bit.
Configure XDMAC_CNDCx.NDVIEW to define the length of the first descriptor.
Enable the End of Linked List interrupt by writing a ‘1’ to XDMAC_CIEx.LIE.
Enable channel x by writing a ‘1’ to XDMAC_GE.ENx. XDMAC_GS.STx is set by hardware.
Once completed, the DMA channel sets XDMAC_CISx.BIS (End of Block Interrupt Status bit) and generates an interrupt. XDMAC_GS.STx is cleared by hardware. The software can either wait for an interrupt or poll the channel status bit.
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