42.7.5.4.4.2 Clock Stretching in Write Mode

The clock is tied low if the internal shifter and TWIHS_RHR is full. If a STOP or REPEATED_START condition was not detected, it is tied low until TWIHS_RHR is read.

The following figure describes the clock stretching in Write mode.

Figure 42-35. Clock Stretching in Write Mode

Note:

At the end of the read sequence, TXCOMP is set after a STOP or after a REPEATED_START + an address different from SADR.
SCLWS is automatically set when the clock stretching mechanism is started and automatically reset when the mechanism is finished.

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