34.16.1.5 SMC Off-Chip Memory Scrambling Register
Note: This register can only be written if the WPEN bit is cleared in the SMC Write
Protection Mode Register (SMC_WPMR).
| Name: | SMC_OCMS |
| Offset: | 0x80 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CS3SE | CS2SE | CS1SE | CS0SE | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SMSE | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
Bits 8, 9, 10, 11 – CSSE Chip Select x Scrambling Enable
| Value | Description |
|---|---|
| 0 | Disable scrambling for CSx. |
| 1 | Enable scrambling for CSx. |
Bit 0 – SMSE Static Memory Controller Scrambling Enable
| Value | Description |
|---|---|
| 0 | Disable scrambling for SMC access. |
| 1 | Enable scrambling for SMC access. |