34.16.1.6 SMC Off-Chip Memory Scrambling Key1 Register
Note:
- ‘Write-once’ access indicates that the first write access after a system reset prevents any further modification of the value of this register.
| Name: | SMC_KEY1 |
| Offset: | 0x84 |
| Reset: | 0x00000000 |
| Property: | Write-once |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| KEY1[31:24] | |||||||||
| Access | |||||||||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| KEY1[23:16] | |||||||||
| Access | |||||||||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| KEY1[15:8] | |||||||||
| Access | |||||||||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| KEY1[7:0] | |||||||||
| Access | |||||||||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 31:0 – KEY1[31:0] Off-Chip Memory Scrambling (OCMS) Key Part 1
When off-chip memory scrambling is enabled, KEY1 and KEY2 values determine data scrambling.