26.4.5.2 RSTC Status Register
| Name: | RSTC_SR |
| Offset: | 0x04 |
| Reset: | 0x00000000 |
| Property: | Read-only |
The register reset value assumes that a general reset has been performed; it is subject to change if other types of reset are generated.
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| SRCMP | NRSTL | ||||||||
| Access | R | R | |||||||
| Reset | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| RSTTYP[2:0] | |||||||||
| Access | R | R | R | ||||||
| Reset | 0 | 0 | 0 | ||||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| URSTS | |||||||||
| Access | R | ||||||||
| Reset | 0 |
Bit 17 – SRCMP Software Reset Command in Progress
When set, this bit indicates that a software reset command is in progress and that no further software reset should be performed until the end of the current one. This bit is automatically cleared at the end of the current software reset.
| Value | Description |
|---|---|
| 0 | No software command is being performed by the RSTC. The RSTC is ready for a software command. |
| 1 | A software reset command is being performed by the RSTC. The RSTC is busy. |
Bit 16 – NRSTL NRST Pin Level
Registers the NRST pin level sampled on each MCK rising edge.
Bits 10:8 – RSTTYP[2:0] Reset Type
This field reports the cause of the last processor reset. Reading this RSTC_SR does not reset this field.
| Value | Name | Description |
|---|---|---|
| 0 | GENERAL_RST | First powerup reset |
| 1 | BACKUP_RST |
Return from Backup mode |
| 2 | WDT_RST | Watchdog fault occurred |
| 3 | SOFT_RST | Processor reset required by the software |
| 4 | USER_RST | NRST pin detected low |
| 5 | – |
Reserved |
| 6 | – |
Reserved |
| 7 | – |
Reserved |
Bit 0 – URSTS User Reset Status
A high-to-low transition of the NRST pin sets the URSTS. This transition is also detected on the MCK rising edge. If the user reset is disabled (URSTEN = 0 in RSTC_MR) and if the interrupt is enabled by RSTC_MR.URSTIEN, URSTS triggers an interrupt. Reading the RSTC_SR resets URSTS and clears the interrupt.
| Value | Description |
|---|---|
| 0 | No high-to-low edge on NRST happened since the last read of RSTC_SR. |
| 1 | At least one high-to-low transition of NRST has been detected since the last read of RSTC_SR. |