4 Appendix 1: PolarFire Transceiver Overview
(Ask a Question)PolarFire FPGA transceivers include all required analog functions for high-speed data transmission between devices over Printed Circuit Boards (PCB) and high-quality cables. They are optimized for low-power operation and are suitable for a variety of device-to-device communication protocols.
The transceiver supports the following embedded PCS:
- 8b10b—The 8b10b mode supports only encodes and
decodes for interface widths of 16, 32,
and 64 bits at the PMA. The 8b10b trans-coders
are protocol independent; in other words, they do not include a protocol-specific word
aligner or word alignment state machine.
Comma-detection is supported in this mode. The serial data must be aligned to comma-alignment boundaries before being used as parallel data. Without proper alignment, the incoming 8b10b data does not decode correctly. The comma character (K28.5) is usually used for alignment, as its 10-bit code is guaranteed not to occur elsewhere in the encoded bitstream. The bit-slip functions in the FPGA fabric can be used to implement the word align or word alignment state machine as required.
- 64b6xb—The 64b66b/64b67b (64b6xb) interface
modes are used for mainly 10 Gbps-based protocols, 10G base interface over Ethernet
(10GBASE-R/KR), and Common Public Radio Interface (CPRI) rates of 9.830 Gbps, and
40GBASE-R standards.
The 64b/66b encoder is used to achieve DC balance and sufficient data transitions for clock recovery. It encodes 64-bit XGMII data and 8-bit XGMII control to 10GBASE-R 66-bit control or data blocks in accordance with Clause 49 of the IEEE® 802.3-2008 specification.
- PIPE—The standard PIPE interface provides a standard interface between the PMA lane and the higher link-level of the PHY. The PHY interface for the PCI Express supports PCIe Gen1/2 and SATA 1.0/2.0/3.0.
- PMA only—Direct access to the PMA without any encoding. The transceiver PMA mode is useful in supporting protocols such as SDI-HD. The PMA Only mode is also used for 1 GbE interfaces. The CoreTSE suite of 1 GbE IPs contain a soft 8b10b encoder/decoder that allows the use of either the transceiver, or the I/O CDR for implementing this standard.
- PCIe—Fully embedded PCIe Gen1/Gen2 root-port or endpoint subsystem (PCIESS) with AXI4 user interfaces with built-in DMA.
For more information, see the PolarFire Family Transceiver User Guide .
The Microchip Libero SoC design software supports configuring transceivers for various modes of operation. The Libero SoC software design tools allow designers to set the configuration needed for a specific operational mode for each transceiver lane.
The software correctly provisions and generates all of the required programming and configuration data used to initialize and bring the transceiver into operation. The transceiver configuration registers are set automatically by the Libero Transceiver Interface configurator. These registers must be left at the default values set by the configurator, except for use cases that explicitly request different values.