8 Appendix 5: References
(Ask a Question)This section lists documents that provide more information about the Multi-rate Transceiver and IP cores used in the reference design.
- For more information about dynamic rate change of transceivers, see AN4592: PolarFire FPGA Dynamic Reconfiguration Interface Application Note .
- For information about PolarFire transceiver blocks, PF_XCVR, PF_TX_PLL, and PF_XCVR_REF_CLK, see PolarFire Family Transceiver User Guide .
- For more information about CCC, see PolarFire Family Clocking Resources User Guide .
- For more information about Libero, ModelSim, and Synplify, see the Libero SoC Documentation web page.
- For more information about device and memory initialization, see PolarFire Family Power-Up and Resets User Guide .
- For more information about SmartDebug features, see AN4594: Debugging PolarFire FPGA Using SmartDebug Application Note .
- For more information about PolarFire FPGA Evaluation Kit, see UG0747: PolarFire FPGA Evaluation Kit User Guide .
- For more information about CoreUART, see CoreUART Handbook. This user guide can be downloaded from Libero SoC Catalog.