A polling routine can be implemented to optimize time‑sensitive applications that would
not prefer to wait the fixed maximum write cycle time (tWC). This method
allows the application to know immediately when the write cycle has completed to start a
subsequent operation.
Once the internally-timed write cycle has started, a polling routine can be
initiated. This involves repeatedly sending a Read STATUS Register
(RDSR) instruction to determine if the device has completed its
self-timed internal write cycle. If the RDY/BSY bit (bit 0 of
STATUS register) = 1, the write cycle is still in progress. If bit
0 = 0, the write cycle has ended. If the
RDY/BSY bit = 1, repeated
RDSR commands can be executed until the
RDY/BSY bit = 0, signaling that the device
is ready to execute a new instruction. Only the Read STATUS Register
(RDSR) instruction is enabled during the write cycle.Figure 8-3. Polling Flowchart
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