4.1 Functional Description

This section describes the implementation details of the FOC Transformations block implemented in the SmartFusion® 2 System-on-Chip (SoC) Field Programmable Gate Array (FPGA) device.

The FOC Transformations block consists of four transformation blocks (clarke, inverse clarke, park, and inverse park), which share a common math block, which perform addition, subtraction, and multiplication. The entire system is synchronized with a system clock, which is available at sys_clk_i.

Each computation is triggered by a rising edge at the start input signal (start_clarke_i, start_park_i, start_ipark_i, and start_iclarke_i) and a rising edge on the corresponding done signal (clarke_done_o, park_done_o, iclarke_done_o, and ipark_done_o) that indicates the completion of the computation.

The clarke computation is triggered by a rising edge at the start_clarke_i input, and the inputs ia_i and ib_i are sampled at this time. At the end of the computation, the outputs ialpha_o and ibeta_o are valid when the clarke_done_o signal goes high.

The park computation is triggered by a rising edge at the start_park_i input, and the inputs i_alpha_i and i_beta_i are sampled at this time. At the end of the computation, the outputs id_o and iq_o are valid when the park_done_o signal goes high.

The inverse park computation is triggered by a rising edge at the start_ipark_i input, and the inputs vq_iand vd_i are sampled at this time. At the end of the computation, the outputs valpha_o and vbeta_o are valid when the ipark_done_o signal goes high.

The inverse clarke computation is triggered by a rising edge at the start_iclarke_i input, and the inputs valpha_i and vbeta_i are sampled at this time. At the end of the computation, the outputs va_o, vb_o and vc_o are valid when the iclarke_done_o signal goes high.