33.8.7 Software Trigger
| Name: | SWTRIG |
| Offset: | 0x0C |
| Reset: | 0x00 |
| Property: | Write-Protected, Write-Synchronized |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| START | FLUSH | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
Bit 1 – START ADC Start Conversion
Writing this bit to zero will have no effect.
| Value | Description |
|---|---|
| 0 | The ADC will not start a conversion. |
| 1 | The ADC will start a conversion. The bit is cleared by hardware when the conversion has started. Setting this bit when it is already set has no effect. |
Bit 0 – FLUSH ADC Conversion Flush
After the flush, the ADC will resume where it left off; i.e., if a conversion was pending, the ADC will start a new conversion.
Writing this bit to zero will have no effect.
| Value | Description |
|---|---|
| 0 | No flush action. |
| 1 | "Writing a '1' to this bit will flush the ADC pipeline. A flush will restart the ADC clock on the next peripheral clock edge, and all conversions in progress will be aborted and lost. This bit will be cleared after the ADC has been flushed. After the flush, the ADC will resume where it left off; i.e., if a conversion was pending, the ADC will start a new conversion. |