33.8.1 Control A
| Name: | CTRLA |
| Offset: | 0x00 |
| Reset: | 0x00 |
| Property: | Write-Protected |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RUNSTDBY | ENABLE | SWRST | |||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 |
Bit 2 – RUNSTDBY Run in Standby
This bit indicates whether the ADC will continue running in standby sleep mode or not:
| Value | Description |
|---|---|
| 0 | The ADC is halted during standby sleep mode. |
| 1 | The ADC continues normal operation during standby sleep mode. |
Bit 1 – ENABLE Enable
Due to synchronization, there is a delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The value written to CTRL.ENABLE will read back immediately and the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY) will be set. STATUS.SYNCBUSY will be cleared when the operation is complete.
| Value | Description |
|---|---|
| 0 | The ADC is disabled. |
| 1 | The ADC is enabled. |
Bit 0 – SWRST Software Reset
Writing a zero to this bit has no effect.
Writing a one to this bit resets all registers in the ADC, except DBGCTRL, to their initial state, and the ADC will be disabled.
Writing a one to CTRL.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded.
Due to synchronization, there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST and STATUS.SYNCBUSY will both be cleared when the reset is complete.
| Value | Description |
|---|---|
| 0 | There is no reset operation ongoing. |
| 1 | The reset operation is ongoing. |